The embodiments described herein relate in general to the field of computer processing systems. More specifically, the embodiments described herein relate to a heuristic method to control fetching of metadata from a cache hierarchy.
An instruction pipeline in a computer processor improves instruction execution throughput by processing instructions using a number of pipeline stages within the processor, where the multiple pipeline stages can act on different instructions of an instruction stream in parallel. It, therefore, allows faster processor throughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate. Rather than processing each instruction sequentially (finishing one instruction before starting the next), each instruction is split into a sequence of steps such that different steps of the different instructions can be executed in parallel and instructions can be processed concurrently. Issues can occur in the presence of branch instructions.